The large scale integration of semiconductor circuits into a smaller wafer area is generally accompanied by numerous problems. First, the circuits themselves must be scaled or reduced in size so that less wafer area is utilized. For circuits employing the MOSFET technology, the geometric pattern of the masks used in fabricating the circuits can be reduced in size to the extent permitted by current photolithographic techniques. For bipolar transistors, the geometric mask patterns can be reduced in size only to a certain degree because of performance limitations imposed by reduced spacing of the transistor semiconductor regions. Such restrictions limit the severe scaling of bipolar devices, as such type of devices are not surface-operating devices like those of the MOSFET technology. Rather, the operation of bipolar transistors depend on the depth of the transistor semiconductor regions.
A second concern in the large scale integration of circuits is the electrical isolation which must be provided between the various circuits on the wafer. Traditionally, electrical isolation of adjacent circuits was provided by either collector diffused isolation technology, or standard buried collector techniques. Oxide isolation and oxide trench isolation techniques are now commonly employed with MOSFET circuits to provide such electrical isolation. In combining the bipolar and MOSFET semiconductor technologies, the junction isolation technique is wasteful of wafer area, and the attempt to use oxide isolation in bipolar circuits makes substrate biasing difficult. Bipolar circuits, and especially analog circuits utilizing PNP transistors require a substrate contact. When using either field oxide or trench oxide isolation techniques, contact to the substrate has conventionally been made to the backside thereof. Backside processing of wafers requires special packaging techniques, including alloy mounting of the chip to a header to insure adequate substrate contact. The increased product costs attendant with backside processing are apparent.
An additional problem encountered in using oxide trench isolation in bipolar circuits is the parasitic MOSFET device which can be formed by such isolation process, wherein the trench isolation itself forms the gate oxide of the parasitic MOSFET device. With the input of the parasitic device located on one side of the isolation trench, and with the output thereof located on the other side, the electrical isolation provided by the trench may be reduced or even negated.
From the foregoing, it can be seen that a need exists for an improved isolation technique compatible with the fabrication techniques of both the bipolar and MOSFET technologies. An associated need exists for a trench isolation technique which also permits substrate contact to the top side of the wafer, and which functions as a shield to reduce or eliminate the parasitic MOSFET devices.